Presently, electrical testing of fabricated ICs is used to minimize the number of ESD problems that can occur. Unfortunately, correcting design-related problems discovered in silicon, after IC fabrication, is costly, primarily because of the time and expense of regenerating new reticules and fabricating new silicon. Additionally, IC fabrication delays can disrupt customer production and delivery schedules, thereby increasing costs even further. Consequently, it is desirable to ascertain ESD-related problems earlier in the design cycle, prior to IC fabrication.
One mechanism leading to ESD failure involves insufficient connections to ESD protection devices in the IC (e.g., metal too narrow or insufficient number of conductive vias). Another mechanism which can lead to ESD failure in the IC involves power and ground networks having excessive resistance and/or improper connections. Even if a chip- or block-level data base is constructed using previously tested input/output (I/O) cells, there can still be ESD failures due, at least in part, to the manner in which such cells are connected. For example, an I/O cell connection to an ESD power clamp is generally critical to ESD robustness. If that connection is poor, the ESD protection voltage for the IC could be significantly lower than the ESD protection voltage for the I/O cell or the ESD power clamp separately.
Conventional techniques for minimizing ESD device failures include generating a set of standard ESD cells that have been previously characterized. One disadvantage with this approach, however, is that it does not allow for product-specific optimization, and furthermore does not cover the top hierarchy connection into these cells. Additionally, this methodology generally requires substantial time to fabricate and pre-characterize any new cells added to the existing set of standard ESD cells.
Another approach for minimizing ESD device failures in the IC is to utilize a computer-aided design (CAD) infrastructure to verify ESD robustness. For example, ALSIM-ESD is a design automation tool (commercially available from IBM Corporation) to analyze power networks for good ESD performance in a high-volume, highly automated application specific integrated circuit (ASIC) design system. The tool calculates the voltage drop produced in the power network by an ESD discharge event and checks that it remains below prescribed circuit failure voltages. ALSIM-ESD utilizes linearized ESD device models, which is overly optimistic since doing so would neglect device turn-on voltage. This device-based approach increases an impact of model inaccuracies and also makes it more difficult to subdivide the ESD verification problem, as is often desirable in a parallel processing environment.
Accordingly, there exists a need for techniques for verifying ESD device connectivity in an IC device, which do not suffer from one or more of the above-noted problems exhibited by conventional ESD testing and verification methodologies.